The present invention relates to visualization of waveforms for a serial data stream, and more particularly to reference clock recovery from the serial data stream in order to perform “eye” diagram measurements that provide a visual indication of voltage and timing uncertainties associated with the serial data stream.
In serial data communications an “eye” diagram is used to visualize how the signals used to transmit multiple bits of data representing a serial data stream may potentially lead to errors in the interpretation of the data bits. This problem is known as inter-symbol interference. For a realtime “eye” diagram a clock needs to be recovered from the data, which clock is then used to slice the data into bits that are in turn rendered to produce the “eye” diagram. From the “eye” diagram various parameters may be measured, such as “eye” width, “eye” height of transition and non-transition bits, and optimal jitter. The clock recovery is key for slicing the data. The clock may be recovered from the data using a constant clock recovery (CCR) technique as disclosed in U.S. Pat. No. 6,836,738 entitled “Method for Optimized Rendering of Eye Diagrams Synchronized to a Recovered Clock and Based on a Single Shot Acquisition.” In this technique an input signal is acquired, edge timing is measured and then a symbol rate (or unit interval) is estimated. From the edge timing and the estimated symbol rate the clock signal is derived. The drawback of this method, as shown in FIG. 1, is that the resulting “eye” diagram using the recovered clock includes both high and low frequency jitter, with the low frequency jitter (wander) being reflected as jitter.
An emerging technology for data transfer between data storage devices, such as a hard disk and a personal computer (PC), is Serial Attached SCSI (SAS). This interface is a combination of serial data and SCSI (Small Computer System Interface) that has the advantage of data rate speeds up to 3 Gbs (gigabits per second) with reliable data transfer. Unfortunately the requirement for clock recovery as specified by the T.10 Specification Guide for SAS (T10/1601-D Revision 9d, Working Draft for Serial Attached SCSI-1.1 (SAS-1.1), Section 5.3.5.3 “Receiver device eye mask”, published by American National Standards Institute (ANSI) 30 May 2005) is not satisfied by the constant clock recovery technique as taught in the above-mentioned U.S. Pat. No. 6,836,738. To ensure interoperability of the SAS with different manufacturers, the SAS foundation developed a compliance test procedure, one of which is to ensure signal integrity at high speed which is evaluated using the “eye” diagram measurement.
SAS evolved to address the escalating and more complex storage requirements, factors such as larger capacity, density, security, scalability and accessibility that are more critical than ever. Enterprise data communication centers need to (i) be online all the time, (ii) fulfill requests from numerous users simultaneously, (iii) allow for constant growth and expansion and (iv) be maintained while in operation. SAS has the capability of fulfilling these requirements as well as providing the necessary performance and scalability to move data at gigabit speeds—speeds that meet or exceed current storage input/output (I/O) performances found in ATA (Advanced Technology Attachment), SATA (Serial ATA), SCSI or Fibre Channel systems. The application area includes servers, network attached storage (NAS) and storage area network (SAN). The challenge for designers and test houses requires testing the SAS devices and complying with the specification.
There is no direct solution available to run the “eye” diagram measurements for SAS using a recovered clock as described in U.S. Pat. No. 6,836,738. Another way of recovering the clock is by using a first order phase-locked loop (PLL) technique with the incoming data. A PLL is a feedback system containing three basic components—phase detector, loop filter and voltage-controlled oscillator. Simulating the PLL with time domain simulators needs more computer time since thousands of clock cycles need to be simulated to obtain meaningful results.
The PLL is a closed loop mechanism that needs a transfer function that is stable and robust enough to handle jitter and phase shift. The phase of an input signal is extracted by finding the rising or falling edges of the digitized version of the input signal. A digital simulation of an actual hardware PLL circuit may be realized because the input and output signals exist just as digital information. In this case the voltage values at several points in the PLL circuit are expressed in the time domain and are repetitively calculated to derive their time variation. The time interval of the calculation must be sufficiently small to retain the high precision of the simulation. Hence it requires a significant amount of digital processing capability to simulate the actual PLL within a reasonable amount of time.
In the PLL method the PLL phase transfer function is determined by the characteristics of the simulated components. As long as the simulation observes the laws of physics, the resultant transfer function does not differ from that of the actual hardware PLL circuit. Given the time to process the data in the simulation, using this method is not advisable. Hence the first order transfer function to be realized by this method also is not particularly useful.
The recommended procedure according to the T.10 Specification Guide is to extract the clock after passing it through a filter. Note that the first order transfer function may be realized by a convolution method. This method is inherently stable as far as an appropriate impulse response is adopted because it does not include any feedback loop.
What is desired is a clock recovery technique for extracting a wander-tracked clock from a serial data stream in order to perform more accurate “eye” measurements.